基于verilog的带fifo的串口设计
(预估有个628文件)
my_uart_tx.v.bak
3KB
my_uart_rx.v.bak
4KB
ram_buf.v.bak
5KB
_info
5KB
_vmake
29B
_info
2KB
_vmake
29B
_info
8KB
_vmake
29B
_info
5KB
_vmake
29B
_info
6KB
_vmake
29B
_info
14KB
_vmake
29B
_info
3KB
_vmake
29B
_info
6KB
_vmake
29B
uart_test_tb.v.bak
3KB
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