DDR3_SO-DIMM

DDR3 SO-DIMM datesheet JEDECJEDEC Standard no, 21cPage420.18-3Contents7 Test points577.1 Raw Card A Test points577. 2 Raw Card B Test points587. 3 Raw Card c Test points .7.4 Raw Card d Test points···.·.:······.·...;······8 Serial Presence detect definition659 Product Label···6710 SO-DIMM Mechanical SpecificationsI Application note11.1 Max Cin for the stacked SDRAM on Raw Card D x8 2 ranks moduleRevision 1.1Release 20JEDED Standard no, 21cPage420.18-4FiguresBlock Diagram: Raw Card Version A (Populated as 2 ranks ofX16 SDRAMS垂·垂垂音垂垂音音垂垂……122 Block Diagram: Raw Card Version B(Populated as l rank of x& SDRAMS3 Block Diagram: Raw Card version C(Populated as 1 rank ofx16 SDRAMS)…………………144 Block Diagram: Raw Card Version D(Populated as 2 ranks of8 stacked SDRAMs)6 Block Diagram: Raw Card Version F(populated as 2 ranks of5 Block Diagram: Raw Card Version E (on Hold)16x8 SDRAMS)…...,…177 SO-DIMM landing pattern for x88 SO-DIMM landing pattern for x16………199 Example raw Card Component Placement Raw Cards A,B,C,D……………………………2410 Example raw Card Component PlacementRaw Cards e( design on hold).F…….….2512 Clock Net Wiring CKoL, CK[O](Raw Card B).e)11 Clock Net Wiring CK[1: 0, CK1: O](Raw Cards A, C)303113 Clock Net Wiring CK[1: 0], CK[1: O(Raw Card D, PC3-6400, 8500 ONLY)3214 Clock Net Wiring CK[1: 0, CK[1: 0 ( Raw Card e).·...······13315 Clock Net Wiring CK[1: 0], CK[1: 0](Raw Card F)3416 Net Structure Routing for Control nets(Raw Cards A, C),3517 Nct Structurc Routing for Control Ncts18 Net Structure Routing for Control Nets Raw Card d....,.,…,,…,….3719 Net Structure Routing for Control Nets raw Carde3820 Nct Structurc Routing for Control Ncts Raw Card F3921 Net Structure Routing for Address and Command Raw Cards a, B22 Net Structure Routing for Address and Command Raw card c44323 Net Structure Routing for Address and command Raw Card d#1…4424 Net Structure Routing for Address and command raw card d#2…………4525 Net Structure Routing for Address and Command Raw Card e.4626 Net Structure Routing for Address and Command Raw Card F4727 Net Structure Routing for dQ163: 0, DM7: 01, DQS[7: 0, DQS[7: 0( Raw cards a,F)…4928 Net Structure Routing for Data, Data Mask, Data Strobe(RalsB,C)....29 Net Structure Routing for Data, Data Mask, Data Strobe Raw CardD…51…5330 Example 6 layers stack-up for Raw Card A, B2, C25431 Example 8 layers stackup for Raw Card bl, D, F1, F25532 Example 8 layers stackup for Raw Card F35633 Raw card A Front view5734 Raw card a backⅤiew5735 Raw Card B l front view5836 Raw card B1 Back view5837 Raw Card B2 Front View..·······.·.···.··.··.········.··.······.·······.·····..·:····.·.·········.··.···.·Release 20Revision 1.1JEDEC Standard no, 21cPage420.18-5Figures38 Raw card B2 Back view39 Raw Card C Back Side view6040 Raw Card d Front view6141 Raw Card D Back view6142 Raw Card F1 Front view6243 Raw Card f1 Back View)244 Raw card F2 Front view6345 Raw Card F2 Back view6346 Raw card F3 front View6447 Raw card f3BackⅤiew.……6448 Reference Simplified Mechanical Drawing with Keying Position69Revision 1.1Release 20JEDED Standard no, 21cPage420.18-6TablesProduct famiily Attributy2 Raw Cards summary………………83 Absolute Maximum Ratings4 Pin Description……………5 Input/Output Functional Description…106DDR3 SDRAM SO- DIMM Pinout.....….……………117x8 Ball-pattern for 512Mb,lGb,2 Gb and4 Gb ddr3 SDRAMS(TopⅤiew).………,208 x16 Ball-pattern for 512Mb, 1 Gb, 2Gb and 4Gb DDR3 SDRAMs (Top view)......209 DC Electrical Characteristics ..............................................................................................2 110 DDR3 SDRAM Module Configurations(Reference Designs)11 Input Loading Matrix2312 Gerber file releases…2313 Signal groups..............2614 Module length Matching Rules2715 DQ/DQS Matching…………………2816 Decoupling Capacitor guideline·····.·.····2917 Clock Routing trace Lengths Raw Card A········3018 Clock Routing Trace Lengths Raw Card C.....,,,………3019 Clock Routing Trace Lengths Raw Card B,3120 Clock Routing Trace Lengths Raw Card D…,3221 Clock Routing Trace Lengths Raw Card F3422 Control Routing Tracc Lengths Raw Card A3523 Control routing trace Lengths Raw Card O.,,…………3524 Control Routing Trace Lengths Raw Card B3625 Control Routing26 Control routing trace Lengths Raw Card F…4027 Trace Lengths for address and Command Net structures raw card a4128 Trace Lengths for Address and Command net structures Raw Card B............4229 Trace Lengths for Address and Command Net Structures Raw Card C…………4330 Trace Lengths for Address and Command Net structures raw Card d #14431 Trace Lengths for Address and Command Net StructuresRaw cardd#24532 Address/Command routing trace lengths raw Card F4833 Trace Lengths for Data Net Structure Raw Card A.............4934 Trace Lengths for Data Net Structure Raw card F5035 Trace Lengths for Data Net Structure Raw Card B..........…5136 Trace Lengths for Data Net Structure Raw Card c5237 Tracc Lengths for Data Nct Structurc Raw Card D·····.·.·····…5338 PCB Electrical Specifications(Common for all Raw Cards)5439 6 layers Geometry/Impedance for Raw Card A, B2, C5440 8 layers Geometry/Impedance for Raw Card bl, d, F1, F2554l8 layers Geometry/ Impedance Table for F3………..….…………………………5642 Serial Presence Detect Data Example65Release 20Revision 1.1JEDEC Standard no, 21cPage420.18-71 Product DescriptionThis reference specification defines the electrical and mechanical requirements for the PC3-12800 memory module, a204-pin, 800 MHz clock(1600 MT/s data rate), 64-bit wide, Unbuffered Synchronous Double Data Rate 3(DDR3DRAM Small outline Dual In-Line Memory Module(DDr3 SDRAM SO-DIMMs). It also defines a slower version, thePC3-10600, using 667 MHz clock(1333 MT/s data rate)DDR3 SDRAMs, the PC3-8500, using 533 MHz clock(1066MT/S data rate) DDR3 SDRAMs, the PC3-6400 using 400 MHz clock(800 MT/s data rate )DDR3 SDRAMs. TheseDDR3 SDRAM SO-DIMMS are intended for use as main memory when installed in systems such as mobile personalcomputersNote Note: R/CD (2 ranks x8 stacked DRAM)is defined only for PC3-6400& PC3-8500Reference design examples are included that provide an initial basis for Unbuffered so-dimm designs. any modifications to these reference designs must meet all system timing, signal integrity and thermal requirements for 8OOMH7clock rate support. Other designs are acceptable, and all Unbuffered DDR3 SO-DIMM implementations must use simu-lations and lab verification to ensure proper timing requirements and signal integrity in the systemTable 1- Product Family AttributesAttributeValuesNoSO-DIMM OrganizationX64Dimensions(nominal)30.0 mm high, 67.6 mm wide/Mo-268 variation CASo-DIMM Types SupportedUnbufferedPin Count204DDR3 SDRAMs Supported512Mb. 1Gb 2Gb 4GbCapacity256MB. 512MB. 1GB 2GB 4GB 8GBSerial Presence detectConsistent with jedEc latest revision1.5VVoltage Options, nominal1.5VVDDQ3. 0V-36V Von SPDInterfaceSSTL 15Note 1 VDDSPD can not be tied to Vop or VopQ on the DDR3 SO-DIMMRevision 1.1Release 20JEDED Standard no, 21cPage42018-81 Product Description(ContdTable 2- Raw Cards SummaryRaw Card Number of DDR3 SDRAMS/ SDRAM Organiza-Number ofCommentstionRanksA162Maⅹ DRAMWXL=12.3×20.0X8Max dRAMWXL=123x 20.016MaX DRAMWxL=12.3x 20.0Maⅹ DRAMWX L=12.3×20.0x8 Stacked2Pc36400,85000nyE16X8Reserved for planar with square DRAM(Design on HaldPlanar with rectangle DRAM, Max16DRAMWXL=10.5x 14.4Release 20Revision 1.1JEDEC Standard no, 21cPage420.18-92 Environmental RequirementsDDR3 SDRAM Unbuffered So-DIMMs are intended for use in mobile computing environments that have limitedcapacity for heat dissipationTable 3- Absolute Maximum RatingsSymbolParameterRatingUnitsNotesTOPR Operating Temperature(ambient)0to65CSTG Storage Temperature50 toCNote 1 Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device func-tional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability3 ArchitectureTable 4- Pin DescriptionCK[1:0]o] Clock Inputs, positive line 2|DQ(63.01Data Input/outyutputCK1:0]Clock inputs, negative lineDM[: 0] Data MasksCKE[1:0]Clock EnablesDQS[7: 0] Data strobes888RASRow Address strobeDQS[7: 0] Data strobes complementCASColumn Address strobe111RESET Reset PinWEWrite enableTESTLogic Analyzer specific test pin(No connect on SO-DIMM)111S[1:0Chip selectsEVENT Temperature event pinA[9: 01, A11, A[15: 13] Address Inputs14VoDCore and l/o Power18A10/APAddress Input/AutoprechargeGround52A12/BCAddress Input/Burst chopVREFDQBA[20SDRAM Bank addressVREFCAInput/Output ReferenceODT[1:0]On-die termination controlVoDSPD SPD and Temp sensor PowerSerial Presence Detect (SPD)andSCLThermal sensor(TS)Clock Input/1VttTermination voltageSDA SPD and TS Data Input/OutputNCReserved for future useSA[1:0SPD and ts addressTotal: 204Revision 1.1JEDED Standard no, 21cPage420.18-103 Architecture(Cont'd)Table 5-Input/Output Functional DescriptionSymbolPolaFunctioCKO/CKOrossThe system clock inputs. All address and command lines are sampled on the cross point of theCK1/CK1Inputrising edge of CK and falling edge of CK. a Delay Locked Loop ( dll)circuit is driven from theclock inputs and output timing for read operations is synchronized to the input clockCKE[1:0]Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. Bydeactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh modeEnables the associated ddr3 sdram command decoder when low and disables the coms[10]Input Active Low mand decoder when high When the command decoder is disabled. new commands areignored but previous operations continue. Rank 0 is selected by s0; Rank 1 is selected by S1RAS, CASInptout Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS,RAS, and we define the operation to be executed by the sdramBA[20]InputSelects which DDR3 SDRAM internal bank of eight is activatedOD[[Input Active High Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3SDRAM mode registerDuring a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycledefines the column address when sampled at the cross point of the rising edge of CK and fallA[9:0],ing edge of CK. In addition to the column address, AP is used to invoke autoprecharge opera-A1O/APtion at the end of the burst read or write cycle. If AP is high, autoprecharge is selected andA11InputBAO-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During aA12/BCPrecharge command cycle, AP is used in conjunction with BA0-BAn to contral which bank(s)toA[15:13]precharge. If AP is high, all banks will be precharged regardless of the state of BAO-BAninputs If AP is low, then BA0-BAn are used to define which bank to prechargeA12(BC)is sampled during READ and WRITE commands to determine if burst chop(on-thefly will be performed (HIGH, no burst chop; LOW, burst chopped)DQ[63:0]In/OutData Input/Output pinsThe data write masks, associated with one data byte. In Write mode, DM operates as a byteDM[7: 0] Input Active High mask by allowing input data to be written if it is low but blocks the write operation if it is high. InRead mode, DM lines have no effectThe data strobes, associated with one data byte, sourced with data transfers. In Write modeIn/Out Cross the data strobe is sourced by the controller and is centered in the data window In Read modeDQS[7the data strobe is sourced by the ddR3 SDRAMs and is sent at the leading edge of the datawindow. DQS signals are complements, and timing is relative to the crosspoint of respectiveDQS and DQsSupplyPower supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the modREFDQVREFCASupplyReference voltage for sstl 15 inputsThis is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sen-SDAIn/Outsor. A resistor must be connected from the SDa bus line to VdD SPD on the system planar toct as a pullSCLInputThis pin is used to clock data into and out of the sPd EEPRom and temp sensor. A resistormust be connected from the SCL bus line to VdD SPD on the system planar to act as a pull upSA[1: 0]InputAddress pins used to select the Serial Presence Detect and Temp sensor base addressTESTIn/OutThe TESt pin is reserved for bus analysis tools and is not connected on normal memory mod-ules(So-DIMMs)EVENTWire-Active LowThis pin is an output of the thermal sensor to indicate critical module temperature. a resistorOR Outmust be connected from EVEnT bus line to VDDSPD on the system planar to act as a pullupRESETIn Active Low This signal resets the DDR3 SDRAMRelease 20Revision 1.1