afifo_design.rar
(预估有个47文件)
afifo_design
sim
transcript
1KB
work
_vmake
26B
@afifo_wptr_full
_primary.dat
749B
_primary.vhd
478B
verilog.rw
2KB
verilog.asm
13KB
_primary.dbs
2KB
@afifo_sync_r2w
_primary.dat
869B
_primary.vhd
476B
verilog.rw
3KB
verilog.asm
9KB
_primary.dbs
2KB
@afifo_rptr_empty
_primary.dat
752B
_primary.vhd
480B
verilog.rw
2KB
verilog.asm
13KB
_primary.dbs
2KB
@afifo_mem
_primary.dat
2KB
_primary.vhd
652B
verilog.rw
4KB
verilog.asm
21KB
_primary.dbs
4KB
@afifo_sync_w2r
_primary.dat
869B
_primary.vhd
476B
verilog.rw
3KB
verilog.asm
9KB
_primary.dbs
2KB
@afifo
_primary.dat
2KB
_primary.vhd
716B
verilog.rw
4KB
verilog.asm
15KB
_primary.dbs
5KB
_temp
tb
_primary.dat
1KB
_primary.vhd
64B
verilog.rw
4KB
verilog.asm
11KB
_primary.dbs
3KB
_info
1KB
vsim.wlf
32KB
do.do
302B
src
Afifo_sync_w2r.v
5KB
Afifo.v
6KB
Afifo_rptr_empty.v
5KB
Afifo_sync_r2w.v
5KB
Afifo_mem.v
5KB
Afifo_wptr_full.v
5KB
tb
tb.v
2KB
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