library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan_led is port( clk:in std_logic; sg:out std_logic_vector(6 downto 0); bt:out std_logic_vector(7 downto 0)); end; architecture one of scan_led is signal cnt8:std_logic_vector(2 downto 0); signal